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PIC32MX3XX/4XX
FIGURE 14-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
Reset
TMRy
MSHalfWord
TMRx
LSHalfWord
Sync
ADC Event
Trigger (3)
TyIF Event
Flag
0
Equal
32-bit Comparator
PRy
PRx
1
TGATE (TxCON<7>)
Q
Q
D
TGATE (TxCON<7>)
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK (2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of ‘x’ in registers TxCON, TMRx, PRx and TxCK refers to either
Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is available only on Timer2/3 pair.
DS61143G-page 106
? 2010 Microchip Technology Inc.
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